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Once TF is set to 1, the Pentium automatically generates a type 1 interrupt after execution of each instruction The user can write a service routine at the interrupt address vector to display memory locations and/or register to debug a program Single-step mode is nonmaskable and cannot be enabled by the STI (enable interrupt) or disabled by the CLI (disable interrupt) instruction The TF can be set to 1 as follows: PUSHF Save flags MOV BP, SP Move [SP] to [BPI OR [BPI, OlOOH Set TF to one POPF , Pop flags The nonmaskable interrupt is initiated via the Pentium NMI pin It is edge triggered (LOW to HIGH) and must be active for two clock cycles to guarantee recognition It is normally used for catastrophic failures such as a power failure The Pentium obtains the interrupt vector address by automatically executing the INT2 (type 2) instruction internally.

The type 3 interrupt is used for breakpoints and is nonmaskable The user inserts the 1-byte instruction INT3 into a program by replacing an instruction Breakpoints are useful for program debugging The interrupt on overflow is a type 4 interrupt This interrupt occurs if the overflow flag (OF) is set and the INTO instruction is executed The overflow flag is affected, for example, after execution of a signed arithmetic (such as IMUL, signed multiplication) instruction The user can execute an INTO instruction after the IMUL Ifthere is an overflow, an error service routine written by the user at the type 4 interrupt address vector is executed Internal Interrupts The user can generate an interrupt by executing the interrupt instruction INT an The INT nn instruction is not maskable by the interrupt enable flag (IF) The INT nn instruction can be used to test an interrupt service routine for external interrupts.

Type codes 32-255 can be used External Maskable Interrupts The Pentium maskable interrupts are initiated via the INTR pin These interrupts can be enabled or disabled by STI (IF = 1) or CLI (IF = 0), respectively If IF = 1 and INTR active (HIGH) without occurrence of any other interrupts, the Pentium, after completing the current instruction, generates interrupt acknowledge cycles twice, each time for about one cycle. The state of address bit 2 (as decoded from byte enables) distinguishes the first and second interrupt acknowledge cycles During the first interrupt acknowledge cycle, the Pentium drives BE4# (A2 A1 A0 = 100) to LOW, BE7# - BE5# to HIGH, BE3# - BEO# to HIGH, and A3 1 - A3 to LOW.

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During the second interrupt acknowledge cycle, the Pentium drives BEO# (A2 A1 A0 = 000) to LOW, BE7# - BEl# to HIGH, and A3 1 - A3 to LOW This means that BE4# = 0 and BEO# = 1 during the first interrupt acknowledge cycle whereas BE4# = 1 and BEO# = 0 during the second interrupt acknowledge cycle Interrupt acknowledge cycles are terminated when the external system returns BRDY# The first interrupt bus cycle indicates that an interrupt acknowledge cycle is in progress and allows the system to be ready to place the interrupt type code on the next interrupt acknowledge bus cycle Data returned during the first cycle is ignored The Pentium does not obtain information from the bus during the first cycle The external hardware must place the type code on the Do-D, pins of the Pentium s data bus during the second cycle Figure 12.

14 shows a simplified interconnection between the Pentium and the 74HC244 for servicing the INTR Inverted BE4# and BEO# are ORed to enable the 74HC244 to place type code nn (32 to 255) on the Pentium s DO - D7 pins A delay circuit may be required for BRDY#..

If the vibrational state !o, = 0 is the resonant state in the electronic excited state, then the FC factor < uf = 11t:, = 0 > vanishes, whereas for Y:, = 1 being the intermediate state the FC factor < o , = ll";, = 0 > reduces the transition polarizability (Eq 61-8, A- term) and hence the RR intensity to zero The same holds for all vibrational levels p i , 2 2 However, for A # 0 all the relevant FC factors for upward and downward transitions are unequal to zero as indicated schematically in the right panel of Fig 61-1 It has been shown by Myers and Mathies (1987) that for small displacements of the excited state potential surface along the Raman active normal coordinate (small A), the resonance Raman intensity is approximately proportional to A'.